CBMRF001
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CBMRF001 是一款面向 3G 和 4G 基站应用的高性能、高集成度的射频(RF)捷变收发器。该器件的 可编程性和宽带能力使其成为多种收发器应用的理想选择。该器件集 RF 前端与灵活的混合信号基带部分 为一体,集成频率合成器,为处理器提供可配置数字接口,从而简化设计导入。CBMRF001 工作频率范 围为 70 MHz 至 6.0 GHz,涵盖大部分特许执照和免执照频段,支持的通道带宽范围为不到 200 kHz 至 56 MHz。两个独立的直接变频接收器拥有首屈一指的噪声系数和线性度。
CBMRF001【英文排版】
CBMRF001 is a high-performance, highly integrated radio frequency (RF) agile transceiver for 3G and 4G base station applications. The programmability and wideband capability of this device make it an ideal choice for a variety of transceiver applications. The device integrates the RF front-end with a flexible mixed-signal baseband section, incorporates a frequency synthesizer, and provides a configurable digital interface for the processor, thereby simplifying design implementation. The CBMRF001 operates in the frequency range from 70 MHz to 6.0 GHz, covering most licensed and unlicensed frequency bands, and supports a channel bandwidth range from less than 200 kHz to 56 MHz. The two independent direct-conversion receivers feature leading noise figure and linearity. Each receive (RX) subsystem has independent automatic gain control (AGC), DC offset correction, quadrature correction, and digital filtering functions, eliminating the need to provide these functions in the digital baseband. The CBMRF001 also has a flexible manual gain mode that supports external control. Each channel is equipped with two high dynamic range ADCs, which first digitize the received I and Q signals, then pass them through a configurable decimation filter and a 128-tap finite impulse response (FIR) filter, and generate 12-bit output signals at the corresponding sampling rate.
The transmitter adopts a direct-conversion architecture, which can achieve high modulation accuracy and ultra-low noise. This transmitter design results in a TX EVM of less than <−40 dB,leaving considerable system margin for the selection of external power amplifiers. The on-board transmit (TX) power monitor can be used as a power detector to achieve highly accurate TX power measurement. A fully integrated phase-locked loop (PLL) provides low-power fractional-N frequency synthesis for all receive and transmit channels. The design integrates the channel isolation required by frequency division duplex (FDD) systems. All VCO and loop filter devices are also integrated. The circuit uses a 10mm×10mm, 144-pin chip-scale ball grid array package (CSP_BGA). This product can effectively replace AD9361 from ADI.
  • Parameters
  • Features
  • Applications
  • Analog Power Supply Voltages: 3.3V, 1.8V, 1.3V

  • Digital Power Supply Voltage: 1.3V

  • RF 2×2 Transceiver with Integrated 12-bit DAC and ADC

  • Frequency Band: 70 MHz to 6.0 GHz

  • Supports TDD and FDD

  • Tunable Channel Bandwidth: <200 kHz to 56 MHz

  • TX EVM: −40 dB

  • Circuit Interface: CMOS/LVDS Digital Interface

  • ESD Rating: HBM 500V

  • Point-to-point communication system

  • Microcell base station

  • Universal radio sy

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    ANALOG-ENGINEER-CALC — 模拟工程师计算器

    模拟工程师计算器旨在加快模拟电路设计工程师经常使用的许多重复性计算。该基于 PC 的工具提供图形界面,其中显示各种常见计算的列表(从使用反馈电阻器设置运算放大器增益 到为稳定模数转换器 (ADC) 驱动器缓冲器电路选择合适的电路设计元件)。除了可用作单独的工具之外,该计算器还能够很好地与模拟工程师口袋参考书中所述的概念配合使用。

  • 计算工具

    ANALOG-ENGINEER-CALC — 模拟工程师计算器

    模拟工程师计算器旨在加快模拟电路设计工程师经常使用的许多重复性计算。该基于 PC 的工具提供图形界面,其中显示各种常见计算的列表(从使用反馈电阻器设置运算放大器增益 到为稳定模数转换器 (ADC) 驱动器缓冲器电路选择合适的电路设计元件)。除了可用作单独的工具之外,该计算器还能够很好地与模拟工程师口袋参考书中所述的概念配合使用。

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