Core Dialogue | CBM108S085 breaks the dilemma of "synchronization + precision + low power consumption" in multi-channel DAC 1、Multi-channel DAC technology bottleneck The development of multi-channel DAC technology currently focuses on two core challenges. On one hand, industrial applications urgently require solutions combining "multi-channel synchronization with high precision," while traditional discrete approaches struggle due to excessive complexity. For instance, in multi-axis robotic arm control, achieving nanosecond-level synchronization across 8 channels demands discrete DACs that not only occupy excessive PCB space but also face challenges in minimizing inter-channel latency. On the other hand, portable devices like handheld measurement instruments and wearable medical devices face a balancing act between "low power consumption" and "high precision." These devices require both 10-bit resolution and operating currents below 1mA, yet existing products often fail to meet both requirements simultaneously, frequently achieving precision targets while exceeding power limits. Additionally, extreme environmental adaptability remains a technical bottleneck. Applications such as oil exploration and automotive electronics demand wide operating temperatures from-40℃ to 125℃ alongside ESD protection and short-circuit protection. However, some commercial DACs only cover-40℃ to 85℃ temperature ranges, demonstrating insufficient reliability. 2、CBM108S085:10-bit 8-channel DAC pain point solution The CBM108S085 is a 10-bit precision, 8-channel voltage output digital-to-analog converter (DAC) developed by Corebai. This single-chip device integrates rail-to-rail output buffer drive circuits, supports 2.7V~5.5Vwide power ranges, and features low power consumption (540μA no-load current at 3V), dual reset protection (power-on/power-off), independent reference voltage configuration, and daisy-chain cabling capabilities. Compatible with mainstream serial interfaces including SPI, QSPI, and MICROWIRE (up to 40MHz clock rate), it enables direct driver operation without additional amplification circuits. Ideal for portable battery-powered instruments, industrial control systems, and medical devices requiring high precision and reliability in multi-channel voltage regulation. 1、Product overview The CBM108S085 features two compact packaging options: TSSOP16 and QFN16. This single-chip device integrates eight independent DAC channels, each containing a resistor-string DAC core with rail-to-rail output buffering. It delivers full-range voltage output from 0V to reference voltage, enabling direct operation of 2kΩ resistor loads and 1500pF capacitor loads without requiring external operational amplifiers. The chip operates within a 2.7V~5.5V voltage range, delivering ultra-low power consumption under no-load conditions: Typical operating current of 540μA at 3V supply and 600μA at 5V supply. During full-channel sleep mode, current drops to 10μA (with only the power-off reset circuit active), significantly enhancing battery life for portable devices. Additionally, the chip incorporates built-in power-on reset and power-off reset circuits. When the supply voltage rises to the effective range (≥2.7V) or falls below 2.7V, the DAC output remains fixed at 0V to prevent damage from unintended voltage fluctuations in downstream circuits. 2、Core technical characteristics 1）10 high precision and excellent linearity The static linear characteristics of CBM108S085 are optimized for medium and high precision scenarios. The key indicators are as follows (test conditions: VA=2.7-5.5V-, VREF1,2=VA, CL=200pF, TA=25℃): Resolution: 10 bits, corresponding to 1024 voltage output, can achieve the minimum VREF1024) voltage step; Integral nonlinearity (INL): typical value ±0.5LSB, to ensure that the deviation between the output voltage and the theoretical value is in a very small range, no obvious line distortion; Differentiation nonlinear (DNL): the typical value is ±0.05LSB to ensure monotonicity (no loss of code) and avoid jump change of output voltage corresponding to adjacent digital codes; Zero code error (ZE): maximum 15mV, full amplitude error (FSE) maximum-0.1%FSR, gain error (GE) maximum-0.2%FSR, temperature drift characteristics stable (zero code error temperature drift-20μV/℃, gain error temperature drift-1.0ppm/℃), can maintain output accuracy in a wide temperature range from-40℃ to 125℃. CBM108S085 typical INL CBM108S085 typical DNL 2）Low power consumption and flexible sleep control The chip designs multi-level power management scheme for low power consumption scenarios to meet the requirements of different working states: Normal working power consumption: when the input code is 0x800, the typical value of 3V supply current is 540μA, and the typical value of 5V supply current is 600μA; the reference voltage loop current (IST) is 73μA at 3V and 110μA at 5V to avoid additional power waste; Sleep mode control: 8 channels can be configured in sleep mode independently. Three output impedance modes can be selected through serial command (DB[15:12] is set to 1101~1111): High output resistance: avoid the interference of sleep channel to system signal; 2.5kΩ To the ground: adapt to specific load matching requirements; 100kΩ to ground: balance power consumption and load compatibility; when all channels are dormant, the overall power consumption of the chip is reduced to μW class, typical sleep current is only 10μA, significantly extending the battery life of portable devices. 3）Dual independent reference voltage and wide dynamic range CBM108S085 is equipped with two independent external reference voltage inputs (VREF1 and VREF2), which support flexible configuration of output range for different channels: VREF1: provides reference voltage for A~D channel, input range 0.5V~VA (power supply voltage); VREF2: Provides reference voltage for E-H channels with an input range of 0.5V to VA. Users can independently select reference voltages based on channel requirements (e.g., connecting A-D channels to a 2.5V reference source output 0~2.5V, and E-H channels to a 5V reference source output 0-5V), significantly expanding the dynamic range of single-chip outputs without requiring additional voltage divider or amplifier circuits. 4）High reliability and hardware protection mechanism The chip ensures the stability of work through multiple hardware designs and adapts to complex application environments: Dual reset protection: When power-on reset, the DAC output is fixed at 0V after the power supply rises to the effective voltage until receiving a new update command; when power-off reset, the power supply is lower than 2.7V and the output remains 0V to avoid system risks caused by power fluctuations; ESD protection: The human model (HBM) can withstand up to 5000V of electrostatic discharge, the machine model (MM) can withstand 300V, and the charging equipment model (CDM) can withstand 1000V. The test standards of these models ensure that the electronic equipment can resist the damage of electrostatic discharge to the chip. Output short circuit protection: The output buffer has a built-in short circuit protection circuit, and the typical short circuit current is ±20mA (when 3V/5V power supply is used), so as to avoid chip burnout caused by load short circuit. 3、Key electrical parameters 1)Static characteristics (test conditions: VA=2.7-5.5V-, VREF1,2=VA, CL=200pF, TA=25℃) 2) Dynamic characteristics (same test conditions as above) 4、Hardware design points 1. Pin configuration and function (TSSOP16/QFN16) CBM108S085 pin definition is clear, the core pin function and design suggestions are as follows: 2) Power supply and reference voltage design Power supply integrity: if the system power supply ripple>10mVrms, a low differential voltage regulator (LDO, such as output 3.3V CBM1117) should be added in front of VA to ensure stable power supply; Reference voltage accuracy: The accuracy of VREF1 and VREF2 directly determines the output accuracy of DAC. It is recommended to use a reference source with temperature coefficient <10ppm/℃ to avoid the influence of reference drift on output; Wiring specification: analog signal (VOUTA~H, VREF1, VREF) and digital signal (DIN, SCLK, SYNC) should be wired separately. The analog ground and digital ground only converge at the GND pin of the chip to reduce the interference of digital noise on the analog output. 5、Control logic and interface protocol 1）Serial interface frame structure CBM108S085 uses 16-bit frame format (DB[15:0]) to transmit data. The frame structure is defined as follows: DB[15:12]: mode control bit, used to select the command type (write data, mode control, special command, sleep mode); DB[11:0]: Data bit. Since CBM108S085 is a 10-bit DAC, only DB[11:2] is valid (DB[1:0] is invalid bit, which can be set to 0). DB[11] is the most high bit (MSB), and DB[2] is the least high bit (LSB). 2）Output update mode Each DAC channel contains a "data register" (temporary storage of input data) and a "DAC register" (control output voltage), which supports two update modes: WRM (WriteRegisterMode): The default mode when powered on, which only updates the data register and keeps the DAC output unchanged. To update the DAC register of a specified channel, the "Update Select Command" (DB[15:12]=1010, DB[7:0] set 1 for the corresponding channel bit) should be triggered. This mode is suitable for multi-channel synchronous output scenarios; WTM (WriteThroughMode): Data registers and DAC registers are updated synchronously, and DAC output changes immediately. It is suitable for single channel independent control and scenarios requiring fast response. 3）Chrysanthemum chain cascade (expanding channel) When the system needs more than 8 channel DAC, multiple CBM108S085 can be cascaded through chrysanthemum chain mode. Core design points: Hardware connection: The DOUT pin of the first chip (TSSOP16 pin 2/QFN16 pin 16) is connected to the DIN pin of the second chip; all chips share SYNC and SCLK signals; Data transmission: The controller needs to send multiple frames of data in the order of "subsequent chip → front chip" (for example, 3 frames should be sent for 3 cascaded chips) to ensure that each chip receives corresponding data; Synchronous update: When the SYNC signal is pulled up, all chips will update the received frame data to the DAC register at the same time, realizing multi-channel nanosecond synchronous output and reducing the number of system control lines. 3、Typical application scenarios Portable battery-powered instrument: low power consumption (540μA@3V) and small size packaging (QFN16) suitable for handheld multimeter, portable sensor node, sleep mode (10μA) can extend the battery life to more than 72 hours; Digital gain/offset adjustment: 10-bit accuracy and ±0.5LSBINL can be used for amplifier gain calibration or signal offset compensation, such as industrial sensor signal conditioning circuit, without manual fine-tuning; Programmable voltage source/current source: dual reference voltage configuration supports multi-level output (e.g. 0~2.5V/0~5V), can drive proportional valve, LED dimming module, achieve ±0.1% voltage control accuracy; ADC Reference Voltage Source: Featuring low noise (output noise 14μV@30kHz bandwidth) and stable temperature drift characteristics, this device serves as a reference voltage for high-precision ADCs, significantly enhancing sampling accuracy. For instance, in ultrasound imaging systems, the combination of a low-noise reference voltage source with a low-noise driver amplifier can greatly improve overall signal-to-noise ratio (SNR) and total harmonic distortion (THD), thereby boosting the performance of medical imaging equipment. Sensor reference voltage source: 8-channel independent output can provide accurate reference voltage for multiple sensors at the same time, simplifying the power supply design of multi-sensor system.