【 New Product 】 CBM16AD125-16 bit, 125 MSPS, 1.8V, dual channel analog-to-digital converter (ADC)

Released：2023-10-16 02:10:13
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CBM16AD125 is a dual channel, 16 bit, 125MSPS analog-to-digital converter (ADC) that supports multifunctional communication applications that require high performance, low cost, and small size. This dual channel ADC core adopts a multi-level differential pipeline architecture, and each ADC integrates a high bandwidth differential sampling and holding circuit, supporting various input ranges that users can choose from. The chip integrates a reference voltage source internally, making it easy to simplify external design. The duty cycle stabilizer can be used to compensate for changes in the ADC clock duty cycle, ensuring excellent performance of the converter. ADC output data can be directly sent to two external 16 bit output ports, supporting two modes: 1.8VCMOS and LVDS. Flexible power-off options can significantly reduce power consumption. The three wire SPI compatible serial interface can configure various functions of the product. CBM16AD125 adopts a 64 pin QFN package, with a rated temperature range of -40 ℃ to+85 ℃ industrial temperature.

new products

Keywords: 16 bit, dual channel, 1.8V, high-speed ADC, low power consumption

Functional Block Diagram

The functional block diagram of CBM16AD125 is as follows:

Figure 1 Functional Block Diagram

Typical features

Low power consumption: 800mW@125MSPS
Power supply: 1.8V
Output level: 1.8V CMOS or LVDS
Signal to Noise Ratio (SNR)=78dBFS (Fin=70MHz/Fs=125MSPS)
SFDR=88dBc (f) _IN =70MHz/f _S =125MSPS
If the sampling rate reaches 300MHz
Built in 1 to 8 integer input clock divider
Small signal input noise: -153dBm/Hz (200 Ω input impedance/f) _IN =70MHz/f _S =125MSPS
Programmable internal reference voltage source
The maximum range of differential analog input can reach 2Vp-p
Differential analog input bandwidth: 650MHz
Built in clock duty cycle stabilizer
95dB channel isolation/crosstalk
Serial Port (SPI) Control
User configurable built-in testing (BIST) function
Energy saving power-off mode
QFN-64 packaging

Product application

Radar system
Diversity Radio System
Multimode Digital Receiver (3G)
GSM/EDGE/W-CDMA/LTE/CDA2000 WiMAX/TD-SCDMA
I/O demodulation system
Smart antenna system
General Software Radio
Broadband data applications
Ultrasound equipment

Core features

The on-chip disturbance option can improve the spurious dynamic range (SFDR) of analog input signals.
Differential input still has good signal-to-noise ratio (SNR) at input frequencies up to 300MHz.
Using a 1.8V single power supply, the digital output driver is powered by an independent power supply and supports 1.8V CMOS or LVDS output.
The Standard Serial Interface (SPI) can configure various functions of the product, such as multiple data encoding forms (offset binary, binary complement or Gray code), clock DCS enable, power-saving mode, testing mode, and multiple reference voltages.
Compatible with AD9258/AD9268 pins, 16 bit products can be easily converted to 14 bit products.

Typical electrical characteristic diagram

The main parameter characteristic diagram of CBM16AD125 is as follows:

Figure 2. Monotonic FFT (@ f_IN=70MHz)

Figure 3. Relationship between SNR/SFDR and input frequency (f)_IN=70MHz, Dither Off)

Figure 4 The relationship between SFDR, SNR, and input amplitude (@ F _IN =30.1MHz)

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