Key Highlights: Preview

▶ 70 MHz–6.0 GHz wide frequency coverage: Software-adjustable, covering both licensed and unlicensed mainstream frequency bands, with single-chip support for multi-band planning.

▶ Single-chip 2T2R zero-IF architecture: integrates a 12-bit ADC/DAC, AGC, and orthogonal/DC correction within the chip; these calibration steps are eliminated on the baseband side.

▶ High-integration CSP_BGA-144 package: Integrates PLL/VCO and loop filter entirely within the die, effectively reducing the number of external components, simplifying RF design, and features a 10 mm × 10 mm footprint.

I. Product Specifications

*Q1: What is the supported frequency range for CBMRF001?*

A: The device operates at frequencies ranging from 70 MHz to 6.0 GHz, covering most licensed and unlicensed frequency bands; its frequency can be adjusted via the internal frequency synthesizer software, enabling adaptation to different frequency band allocations without the need to replace the external RF chain.

*Q2: What is the maximum signal bandwidth supported by single-channel?*

A: The tunable channel bandwidth range spans from less than 200 kHz to 56 MHz, enabling support for both narrowband private networks and broadband microcell applications. For bandwidth requirements exceeding 56 MHz, it is necessary to evaluate higher-bandwidth solutions or an external architecture.

*Q3: What is the receive/transmit structure like?*

A: The single-chip device adopts a 2T2R (2 transmit, 2 receive) architecture; the two receive channels and the two transmit channels are independent of each other, and both utilize a direct frequency conversion (zero intermediate frequency) architecture.

II. Interface and Hardware Design

*Q4: Which standards does the data interface support?*

A: Dual independent data ports: P0 (transmit TX port) and P1 (receive RX port); in CMOS mode, there are two independent 12-bit parallel buses; in LVDS mode, P0 serves as a 6-bit differential TX input bus, while P1 serves as a 6-bit differential RX output bus; both modes can be switched via software configuration.

*Q5: How to configure the components?*

A: Register configuration and status reading are performed via the SPI bus (SPI_DI / SPI_CLK / SPI_DO / SPI_ENB); the operating state is jointly controlled by pins such as ENABLE, EN_AGC, TXNRX, SYNC_IN, and RESETB, among which TXNRX determines the data port bus direction.

*Q6: What are the power supply requirements?*

A: The analog power supply includes multiple domains (3.3 V, 1.8 V, and 1.3 V), while the digital power supply is 1.3 V; under recommended operating conditions, VDD_GPO = 3.3 V, VDD_INTERFACE = 1.8 V, and all other VDDx = 1.3 V. Each power domain should be physically separated in layout and connected via local bypass paths.

*Q7: How is the reference clock handled?*

A: Connect to the reference clock via XTALP/XTALN (typically 40 MHz); the reference frequency can be multiplied internally to accommodate different RF frequencies. When using an external clock source, connect to XTALN and leave XTALP floating.

III. Performance Specifications

*Q8: Key performance indicators for the receiving channel?*

A: Typical RX noise figure: 2.8 dB at 800 MHz, 4 dB at 5.5 GHz; gain ranges from approximately 70 dB (800/2300 MHz) to 62 dB (5.5 GHz), in 1-dB steps; third-order input intercept point: approximately −11 dBm (800 MHz) / −4 dBm (5.5 GHz).

*Q9: Key performance indicators for the transmission channel?*

A: Typical maximum output power: 8 dBm at 800 MHz, 7 dBm at 2.4/5.5 GHz (50 Ω load); TX EVM better than –40 dB; power control range: 90 dB, resolution: 0.25 dB; features an on-chip transmit power monitor that supports real-time transmit power calibration.

*Q10: How does channel isolation perform?*

A: The typical isolation between transmit channels (TX1↔TX2) and receive channels (RX1↔RX2) is 50–55 dB, meeting the fundamental requirements for transmit–receive and channel-to-channel isolation in FDD systems.

IV. Packaging and Applications

*Q11: Packaging and dimensions?*

A: Utilizes a 10 mm × 10 mm, 144-pin chip-scale ball grid array package (CSP_BGA, BGA-144). The exposed solder pads on the bottom side must be soldered to the large-area ground plane of the PCB to ensure both thermal dissipation and ground connection.

*Q12: How are multiple slices synchronized?*

A: The SYNC_IN pin enables synchronization of digital clocks among multiple CBMRF001 devices; array systems with more than 2T2R units require cascading multiple devices and utilize this signal for clock alignment.

*Q13: Operating temperature range?*

A: Operating temperature range: −40 °C to +85 °C (industrial-grade); maximum junction temperature: 110 °C; for high-density board-level layouts, the package thermal resistance and power dissipation margin must be verified.

*Q14: What is the relationship to the imported equivalent solution?*

A: This device can be compared with mainstream imported RF transceiver solutions in the same category; its interface and functional specifications are similar, facilitating in-situ replacement in existing designs and enabling evaluation of domestic substitution options, thereby reducing supply chain risks.

*Q15: Which scenarios require careful assessment?*

A: Single-channel bandwidth upper limit is 56 MHz; for ultra-wideband Massive MIMO or scenarios requiring bandwidth greater than this value, a separate evaluation is required.

Selection Recommendations

The CBMRF001 is a high-integration 2T2R RF transceiver designed for applications such as microcellular, point-to-point communication, and software-defined radio (SDR) systems. When the target system operates within the frequency range of 70 MHz–6.0 GHz, has a single-channel bandwidth not exceeding 56 MHz, and requires high integration, flexible digital interfaces, and a simplified peripheral component design, the CBMRF001 can be considered as a preferred RF transceiver solution. For applications involving wider bandwidths or larger array sizes, it is recommended to conduct a further evaluation based on specific system requirements.